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| CXD1170M 6-bit 40MSPS High Speed D/A Converter For the availability of this product, please contact the sales office. Description The CXD1170M is a 6-bit 40MHz high speed D/A converter. The adoption of a current output system reduces power consumption to 80mW (200 load at 2Vp-p output). This IC is suitable for digital TV and graphic display applications. Features * Resolution 6-bit * Max. conversion speed 40MSPS * Non linearity error within 0.1LSB * Low glitch noise * TTL CMOS compatible input * +5V single power supply * Low power consumption 80mW (200 load at 2Vp-p output) 24 pin SOP (Plastic) Structure Silicon gate CMOS IC Function 6-bit 40MHz D/A converter Block Diagram and Pin Configuration NC NC 1 2 24 DVDD 23 DVDD 22 AVDD DECODER 21 20 LATCHES CURRENT CELLS IO IO (LSB) D0 3 D1 D2 4 5 D3 6 D4 D5 7 8 DECODER 19 AVDD 18 AVDD 17 VG 16 VREF BLK 9 DVSS 10 VB 11 CLK 12 CLOCK GENERATOR CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR 15 IREF 14 AVSS 13 DVSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E89X37B6X-PS CXD1170M Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD * Input voltage VIN * Output current IOUT * Storage temperature Tstg Recommended Operating Conditions * Supply voltage AVDD, AVSS DVDD, DVSS * Reference input voltage VREF * Clock pulse width Tpw1 Tpw0 * Operating temperature Topr 7 VDD to VSS 15 -55 to +150 V V mA C 4.75 to 5.25 4.75 to 5.25 2.0 12.5 (Min) 12.5 (Min) -20 to +75 V V V ns ns C Pin Description and I/O Pins Equivalent Circuit No. Symbol Equivalent circuit DVDD 3 Description 3 to 8 D0 to D5 to 8 DVSS DVDD Digital input 9 BLK 9 Blanking pin No signal at "H" (Output 0V) Output condition at "L" DVSS DVDD DVDD 11 VB 11 Connect a capacitor of about 0.1F DVSS DVDD 12 CLK 12 Clock pin Moreover all input pins are TTL-CMOS compatible DVSS 10, 13 14 DVSS AVSS -2- Digital GND Analog GND CXD1170M No. 15 Symbol IREF Equivalent circuit AVDD AVDD Description Connect a resistance 16 times "16R" that of output resistance value "R" 15 AVDD AVSS 16 AVDD 16 VREF Set full scale output value AVSS 17 17 18, 19, 22 VG AVSS Connect a capacitor of about 0.1F Analog VDD AVDD AVDD 20 IO 20 Current output pin Voltage output can be obtained by connecting a resistance AVSS AVDD 21 IO 21 Inverted current output pin Normally dropped to analog GND AVSS 23, 24 DVDD Digital VDD Eleoctrical Characteristics Item Resolution Symbol n (fCLK = 40MHz, VDD = 5V, ROUT = 200, VREF = 2.0V, Ta = 25C) Measurement conditions Min. Typ. 6 40 0.5 -0.3 -0.1 1.85 1.95 10 0.5 0.1 2.05 15 1 14.3MHz, at COLOR BAR DATA input 13 14.5 16 5 -5 5 10 10 ROUT = 75 -3- 30 Max. Unit bit MSPS MHz LSB LSB V mA mV mA A A ns ns ns pV-s Maximum conversion speed fMAX Minimum conversion speed fMIN Linearity error Differential linear error Full scale output voltage Full scale output current Offset output voltage Power supply current Digital input current Setup time Hold time Propagation delay time Glitch energy EL ED VFS IFS VOS IDD High level IIH Low level IIL tS tH tPD GE CXD1170M Maximum conversion speed test circuit 6bit COUNTER with LATCH 3 D0 (LSB) * * * 4 8 D5 IO 20 200 OSCILLOSCOPE AVDD VG 17 0.1 VREF 16 2V AVss 1k 9 BLK 0.1 CLK 40MHZ SQUARE WAVE 11 VB 12 CLK IREF 15 3.3k DC characteristics test circuit 3 D0 (LSB) CONTROLLER * * * 4 8 D5 IO 20 200 DVM AVDD VG 17 0.1 VREF 16 2V AVss 1k 9 BLK 0.1 CLK 40MHZ SQUARE WAVE 11 VB 12 CLK IREF 15 3.3k Propagation delay time test circuit 3 D0 (LSB) * * * 4 8 D5 IO 20 200 OSCILLOSCOPE AVDD VG 17 0.1 VREF 16 1k AVss CLK 10MHZ SQUARE WAVE FREQUENCY DEMULTIPLIER 9 BLK 0.1 11 VB 12 CLK IREF 15 3.3k Setup hold time and glitch energy test circuit 6bit COUNTER with LATCH DELAY CONTROLLER CLK 1MHZ SQUARE WAVE DELAY CONTROLLER 3 D0 (LSB) * * * 4 8 D5 IO 20 75 OSCILLOSCOPE AVDD VG 17 0.1 VREF 16 1V AVss 1k 9 BLK 0.1 11 VB 12 CLK IREF 15 1.2k -4- CXD1170M Operation Timing Chart TPW1 TPW0 CLK tS tH tS tH tS tH DATA tPD 100% D/A OUT tPD tPD 50% 0% Application Circuit DVDD 1 2 (LSB) 3 4 6bit DIGITAL INPUT 5 6 7 8 9 10 0.1 11 12 14 13 DGND 22 21 AGND 20 200 19 18 0.1 17 2V 16 15 3.3k 1k D/A OUT 24 23 AVDD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. I/O Chart (when full scale output voltage at 2.00V) Input code MSB 1111 : 1000 : 0000 LSB 11 00 00 Output voltage 2.0V 1.0V 0V -5- CXD1170M Notes on Operation * How to select the output resistance The CXD1170M is a D/A converter of the current output type. To obtain the output voltage connect the resistance to IO pin. For specifications we have: Output full scale voltage VFS = less than 2.0 [V] Output full scale current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS x R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF. In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF x 16R/R'. R is the resistance connected to IO while R' is connected to IREF. Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. * Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. * VDD, VSS To reduce noise effects separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of about 0.1F, as close as possible to the pin. * Latch up AVDD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON. -6- CXD1170M Output full scale voltage vs. Reference voltage 200 Output resistance vs. Glitch energy VFS - Output scale voltage [V] 2.0 Glitch energy [pV-s] VDD = 5.0V R = 200 16R = 3.3k Ta = 25C 1.0 2.0 100 1.0 0 100 Output resistance [] 200 VREF - Reference voltage [V] Output full scale voltage vs. Ambient temperature Output full scale voltage [V] 2.0 1.9 VDD = 5.0V VREF = 2.0V R = 200 16R = 3.3k Ta = 25C 0 -25 0 25 50 75 Ambient temperature [C] -7- CXD1170M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 - 0.1 24 13 + 0.4 1.85 - 0.15 0.15 + 0.3 5.3 - 0.1 7.9 0.4 + 0.2 0.1 - 0.05 0.45 0.1 1.27 + 0.1 0.2 - 0.05 0.12 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING COPPER ALLOY / 42ALLOY 0.3g -8- 0.5 0.2 1 12 6.9 |
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